In order to provide increased functional capability, integrated circuit devices are continually redesigned to smaller and smaller geometric dimensions. Although reducing transistor dimensions increases the functional performance of an integrated circuit, transistors can suffer a loss of performance when scaled to dimensions below one micron. The performance loss is especially acute in complementary-metal-oxide-semiconductor (CMOS) devices, which contain large numbers of diffused junctions.
As CMOS devices are continually scaled to dimensions below one micron, device reliability dictates a concomitant reduction in the power supply voltage. However, the reduction in physical dimensions coupled with the reduction in power supply voltage effectively reduces the transistor current. At reduced current levels, parasitic capacitances, such as drain junction capacitance and gate overlap capacitance, become significant factors contributing to low operating speed in transistor devices.
Performance degradation arising from short-channel effects represents an additional problem encountered as device dimensions are scaled below one micron. In particular, threshold voltage instability and current leakage can occur across the channel region of a metal-oxide-semiconductor (MOS) transistor having an effective channel length below one micron. Short-channel effects are typically addressed by selectively doping portions of the channel region, and by providing source and drain extensions adjacent to the channel region. Additionally, the substrate doping is often adjusted to compensate for the additional channel doping used to combat the short-channel effects.
While increased doping of the substrate and the channel region forestalls the onset of short-channel behavior in sub-micron CMOS devices, the additional dopants increase parasitic capacitances in the device. One solution to the parasitic capacitance problem is the fabrication of transistor devices in a silicon-on-insulator (SOI) substrate. The buried oxide layer of the SOI substrate effectively separates the junctions associated with the transistors from the underlying semiconductor substrate. The junction capacitance is reduced by increasing the separation distance between regions of high dopant concentration. For example, the buried oxide layer in an SOI device separates active transistor regions from the silicon substrate, thus reducing junction capacitance. Although buried oxide layers are effective at reducing junction capacitance, SOI substrates are expensive to produce and increase the unit cost of CMOS devices fabricated in SOI substrates. Accordingly, a need existed for a CMOS device and fabrication process using conventional silicon technology, yet achieving reduced junction capacitance at device geometries below one micron.